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Jun
Industry-leading 144-port PCIe Gen5 switch with N+1 linear non-blocking architecture — built for AI clusters, hyperscale data centers, and intelligent robotics
Hsinchu, Taiwan — June 2026 — XinPal (芯夥科技), a Singapore-incorporated AI infrastructure IC design company with R&D operations in Hsinchu, Taiwan, today announced its debut at COMPUTEX 2026 (Booth A0912). XinPal showcased the XPS50144, its flagship PCIe Gen5 x16 Fabric Switch, alongside its 3D DRAM and C2C Memory IP — two products addressing the interconnect and memory bandwidth bottlenecks that are increasingly becoming the defining performance ceiling of large-scale AI infrastructure.
The Inflection Point: When Interconnect Becomes the Bottleneck
The AI infrastructure industry is undergoing a structural shift. For years, scaling AI performance meant adding more compute and memory. That equation has changed. As AI clusters grow from hundreds to tens of thousands of accelerators — spanning servers, racks, and data centers — the interconnect fabric between them has emerged as the decisive bottleneck. GPU utilization, training stability, inference tail latency, and total system efficiency are all increasingly determined not by compute alone, but by how fast and efficiently data moves across the system.
This shift is structural, not cyclical. Generative AI and agentic workloads demand larger context windows, more complex memory access patterns, and tighter coordination across heterogeneous accelerators. The question is no longer whether interconnect matters — it is which architecture can scale without introducing new constraints.
Existing PCIe switch solutions are built on butterfly or tree topologies that introduce cumulative multi-hop latency and hard scalability ceilings. XinPal’s N+1 linear non-blocking architecture eliminates intermediate hops entirely, delivering deterministic, low-latency data paths across up to 144 PCIe Gen5 x16 ports — a configuration purpose-built for the next generation of AI cluster scale.
Product Highlights
XPS50144 — PCIe Gen5 Fabric Switch
• 144-port PCIe Gen5 x16 full-bandwidth fabric switch — the highest port-count configuration in its class
• N+1 linear non-blocking architecture — no multi-hop penalty, deterministic low latency at scale
• Multi-protocol support: PCIe 5.0, UALink, CXL, and C2C in a single device
• Targets AI GPU clusters, hyperscale data centers, and intelligent robotics platforms
• Available as chip and GDSII IP license — enabling direct integration into partner SoC roadmaps
3D DRAM / C2C Memory IP
• Chiplet-based high-bandwidth memory expansion for AI accelerators
• C2C interconnect enables tight die-to-die integration between logic and memory
• Optimized for LLM inference workloads requiring large, fast, and flexible memory pools
• Supports disaggregated memory architectures for cost-efficient, scalable AI system design
“We are building for the moment when interconnect becomes the defining layer of AI infrastructure — and that moment is now. As AI clusters scale beyond what any single machine or rack can contain, the fabric connecting accelerators, memory, and storage determines whether a system can perform at its theoretical ceiling or falls short of it. XinPal’s linear architecture and multi-protocol design are a direct answer to that constraint. We are not building another switch. We are building the interconnect foundation for next-generation AI factories.”
— [Eric Tsai, CEO], XinPal
Industry Engagement at COMPUTEX 2026
During the five-day exhibition, XinPal’s Booth A0912 attracted engineers, product managers, and executives from the semiconductor, AI systems, cloud infrastructure, and robotics sectors across Asia, Japan, Korea, Europe, and North America. The company conducted technical briefings on the XPS50144 architecture and held partnership discussions spanning co-development, IP licensing, and system integration — reflecting strong industry interest in next-generation AI interconnect solutions.
